The disclosed embodiments relate to a latency control circuit, and more particularly, to a technology for increasing accuracy of a latency control circuit.
Diverse semiconductor chips do not operate alone but transfer/receive signals to/from other neighboring semiconductor chips to operate. For example, when a memory controller applies a read command to a semiconductor memory device, the semiconductor memory device transfers data stored therein to the memory controller. However, the semiconductor memory device cannot transfer its data to the memory controller instantly after it receives the read command because time is required for the semiconductor memory device to call for and output the stored data inside.
For a first semiconductor chip A and a second semiconductor chip B to interact, it takes a predetermined waiting time for the first semiconductor chip A to request the second semiconductor chip B to perform a particular operation, and the second semiconductor chip B to perform the requested operation in response to the request. This waiting time is referred to as latency. For example, when CAS (column address strobe) latency (CL) is set at 7 clocks/clock cycles and the memory controller applies a read command to a semiconductor memory device, the semiconductor memory device transfers data to the memory controller 7 clocks after the application time point of the read command.
A circuit for controlling such latency that enables cooperation between the first semiconductor chip A and the second semiconductor chip B is referred to as latency control circuit.
FIG. 1 illustrates a conventional latency control circuit and its peripheral units. Referring to FIG. 1, an input signal INPUT inputted to an input pad 101 represents a signal inputted to a semiconductor chip, and a target circuit 140 is a circuit that performs an operation (for instance, an operation referred to hereinafter as “X” operation) in response to the input signal INPUT. Delay A 110 represents a delay that the input signal INPUT goes through inside the chip until it arrives at a latency control circuit 120, and delay B 130 represents a delay that the input signal INPUT outputted from the latency control circuit 120 goes through until it arrives at a target circuit 140.
When it is assumed that the latency between the input signal INPUT and the X operation is N, the target circuit 140 should perform the X operation at N clocks after the input signal INPUT is applied to the input pad 101. Therefore, the input signal INPUT inputted to the input pad 101 should arrive at the target circuit 140 exactly at N clocks thereafter. The latency control circuit 120 controls a delay value of the input signal INPUT in such a manner that the input signal INPUT arrives at the target circuit 140 at the time corresponding to the latency accurately.
As described before, the latency control circuit 120 is desired to control the delay value of the input signal INPUT so that the input signal INPUT inputted to the inside of the chip arrives at the target circuit 140 at N clocks later corresponding to the latency. However, there are many variables. The delay values of the delay A 110 and the delay B 130 continue to be changed as the process, voltage, and temperature (PVT) conditions are changed inside the chip. Therefore, there is a concern that the latency control circuit 120 does not transfer the input signal INPUT to the target circuit 140 at the exact time corresponding to the latency.